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HD647180X (1/5) IL00D
C-MOS 8-BIT MICRO PROCESSING UNIT
--TOP VIEW--
64 63 62 61 60 59 58 57 56 55 54 53 21 51 50 49 48 47 46 45 44 43 42 41
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
GND
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
GND
GND
VDD
GND VDD
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
HD647180X (2/5) MODE 0 MODE 1 MODE 2 PROM MODE PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 : : : : HD643180X, HD647180X HD641180XF6, HD643180X, HD647180X, HD641180X-8L-FP80B HD643180X, HD647180X HD647180X MODE 1 SIGNAL MODE 2 SIGNAL PROM MODE SIGNAL A9 NC NC NC NC A0 A1 A2 A3 GND A4 A5 A6 A7 A8 NC A10 A11 A12 A13 A14 OE CE NC NC NC VDD NC GND O0 O1 O2 O3 O4 O5 O6 O7 GND NC NC
I/O I I I I I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O -- I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I I
MODE 0 SIGNAL
NMI INT0 INT1 INT2
PE4 PC0 PC1 PC2 PC3 GND PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 TOUT1 VDD PE3 GND PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 GND PG0/AN0 PG1/AN1
I/O I I I I O O O O O -- O O O O O O O O O O O O O O O O -- O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I I
NMI INT0 INT1 INT2
ST A0 A1 A2 A3 GND A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 TOUT1 VDD A19 GND D0 D1 D2 D3 D4 D5 D6 D7 GND PG0/AN0 PG1/AN1
I/O I I I I O O O O O -- O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O -- I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I I
NMI INT0 INT1 INT2
ST A0 A1 A2 A3 GND A4 A5 A6 A7 A8/PD0 A9/PD1 A10/PD2 A11/PD3 A12/PD4 A13/PD5 A14/PD6 A15/PD7 A16/PE0 A17/PE1 A18/PE2 TOUT1 VDD A19/PE3 GND D0 D1 D2 D3 D4 D5 D6 D7 GND PG0/AN0 PG1/AN1
I/O O -- -- -- -- O O O O -- O O O O O -- O O O O O I I -- -- -- -- -- -- O O O O O O O O -- -- --
HD647180X (3/5) PIN No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 MODE 0 SIGNAL PG2/AN2 PG3/AN3 PG4/AN4 PG5/AN5 MODE 1 SIGNAL PG2/AN2 PG3/AN3 PG4/AN4 PG5/AN5 MODE 2 SIGNAL PG2/AN2 PG3/AN3 PG4/AN4 PG5/AN5 PROM MODE SIGNAL NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND NC MP1 MP0 XTAL EXTAL VDD NC NC NC VPP
I/O I I I I O I I O I I/O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O -- O I I I I -- I/O I/O I/O I
RTS0 CTS0 DCD0
TXA0 RXA0 CKA0/DREQ0 TOUT2 TOUT3 IC TXA1/PA0 RXA1/PA1 CKA1/TEND0/PA2 TXS/PA3 RXS/CTS1/PA4 CKS/PA5 DREQ1/PA6 TEND1/PA7 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND O MP1 MP0 XTAL EXTAL VDD PE7 PE6 PE5
RESET
I/O I I I I O RTS0 I CTS0 I DCD0 TXA0 O RXA0 I I/O CKA0/DREQ0 TOUT2 O TOUT3 O IC I TXA1/PA0 I/O RXA1/PA1 I/O I/O CKA1/TEND0/PA2 TXS/PA3 I/O I/O RXS/CTS1/PA4 CKS/PA5 I/O I/O DREQ1/PA6 I/O TEND1/PA7 O HALT O REF O IOE O ME E O O LIR O WR O RD GND -- O O MP1 I MP0 I XTAL I EXTAL I VDD -- I WAIT O BUSACK I BUSREQ I RESET
I/O I I I I O I I O I I/O O O I I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O -- O I I I I -- I O I I
RTS0 CTS0 DCD0
TXA0 RXA0 CKA0/DREQ0 TOUT2 TOUT3 IC TXA1/PA0 RXA1/PA1 CKA1/TEND0/PA2 TXS/PA3 RXS/CTS1/PA4 CKS/PA5 DREQ1/PA6 TEND1/PA7
HALT REF IOE ME
E
LIR WR RD
GND O MP1 MP0 XTAL EXTAL VDD
WAIT BUSACK BUSREQ RESET
I/O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I I I I -- -- -- -- --
HD647180X (4/5) INPUT AN0 - AN5
BUSREQ CTS0, CTS1 DCD0, DCD1 DREQ0, DREQ1
EXTAL IC INT0 - INT2 MP0, MP1
NMI RESET
PG0 - PG5 RXA0, RXA1 RXS XTAL OUTPUT A0 - A19 BUSACK E
: : : : : : : : : : : : : : :
ANALOG INPUT BUS REQUEST CLEAR TO SEND GOR ASYNCHRONOUS SCI CHANNEL n (n = 0 OR 1) DATA VARRIER DETECT FOR ASYNCHRONOUS SCI CHANNEL n (n = 0 OR 1) DMA REQUEST FOR CHANNEL n (n = 0 OR 1) EXTERNAL CLOCK INPUT CAPTURE INTERRUPT MOD PROGRAM NON-MASKABLE INTERRUPT RESET 6-BIT INPUT OF PORT G RECEIVE DATA FOR ASYNCHRONOUS SCI CHANNEL n (n = 0 OR 1) RECIEVE DATA FOR SERIAL I/O PORT CLOCK
: : : : IOE : LIR : ME : RD : REF , RTS1 : RTS0 ST : , TEND1 : TEND0 TOUT1 - TOUT3 : TXA0, TXA1 : TXS : : WR O : INPUT/OUTPUT CKA0, CKA1 CKS D0 - D7 PA0 - PA7 PB0 - PB7 PC0 - PC7 PD0 - PD7 PE0 - PE7 PF0 - PF7
ADDRESS BUS BUS ACKNOULEDGE ENABLE I/O ENABLE LOAD INSTRUCTION REGISTER MEMORY ENABLE READ REFRESH REQUEST TO SEND FOR ASYNCHRONOUS SCI CHANNEL n (n = 0 OR 1) STATUS TRANFER END FOR CHANNEL n (n = 0 OR 1) TIMER OUT TRANSFER DATA FOR ASYNCHRONOUS SCI CHANNEL n (n = 0 OR 1) TRANSFER DATA FOR SERIAL I/O PORT WRITE SYSTEM CLOCK
: : : : : : : : :
CLOCK FOR ASYNCHRONOUS SCI CHANNEL n (n = 0 OR 1) CLOCK FOR SERIAL I/O PORT DATA BUS 8-BIT INPUT/OUTPUT OF PORT A 8-BIT INPUT/OUTPUT OF PORT B 8-BIT INPUT/OUTPUT OF PORT C 8-BIT INPUT/OUTPUT OF PORT D 8-BIT INPUT/OUTPUT OF PORT E 8-BIT INPUT/OUTPUT OF PORT F
HD647180X (5/5)
*1 HD641180XF6 HD641180X-8L-FP80B HD643180X HD647180X
PF0 - PF7 /D0 - D7
PG0/AN0
PG1/AN1
PG2/AN2
PG3/AN3
PG4/AN4
PG5/AN5
PC0 - PC7,PD0 - PD7, PE0 - PE3/A0 - A19
: : : MASK ROM : PROM (16kB)
TOUT3
TOUT2
IC
39
40
41
42
43
44
52
53
30 - 37
6 - 9, 11 - 25, 28
51
71
o
74 ADDRESS BUFFER TIMING GEN 76
XTAL EXTAL
ANALOG COMPARATOR (6CH)
MMU
DATA BUFFER
16-BIT PROGRAMABLE TIMER
73
*1
RAM (512B)
72 5 79 78
BUS STATE CONTROL
MP0 MP1 PE4/ST PE5/BUSREQ PR6/BUSACK PE7/WAIT RESET PB7/HALT PB6/REF PB5/IOE PB4/ME PB3/E PB2/LIR PB1/WR PB0/RD NMI INT0 INT1 INT2
77 80 62 63 64 65 66 67 68 69
PORT G PORT F PORT E PORT D PORT C PORT B PORT A
ADDRESS BUS (16-BIT)
CPU
DATA
BUS (8-BIT)
INTERRUPT
CLOCKED SERIAL I/O BOARD
ASCI (CHANNEL1)
ASCI (CHANNEL 0)
16-BIT RELOAD TIMER (2CH)
1 DMAV (2CH) 2 3 4
55
56
54
47
46
45
49
50
48
61
59
58
57
26
PA7/TEND1
60 PA6/DREQ1
PA4/RXS/CTS1
PA5/CKS
PA3/TXS
PA2/CKA1/TEND0
CKA0/DREQ0
PA1/RXA1
PA0/TXA1
DCD0
CTS0
RTS0
RXA0
TXA0
TOUT1

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